Field effect transistors (FETs) are transistors in which the voltage at a gate is used to create a field that either facilitates or prevents conduction between a source terminal and a drain terminal. Multiple FETs connected in parallel have previously been utilized in electrical switch devices to reduce the overall resistance of such devices. However, such designs had the disadvantage that one of the FETs connected in parallel would be the first to experience the entire commutation stress of the switch upon activation and likewise one of the FETs would experience the entire commutation stress of the switch upon deactivation. Therefore, each FET had to be sufficiently large to handle the entire commutation stress and the reduction in resistance that could be achieved through the use of parallel FETs was limited.
The subject matter of the present disclosure is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.